Loading Events

Synopsys: Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges

July 14

PCIe, the most popular interconnect in compute, AI and storage systems, is now offering faster data rate, higher performance, lower power and lower latency than the previous generation. Because of these reasons and the addition of PAM-4 signaling, challenges such as signal integrity, power integrity, implementation, IP integration and more must be considered when designing 64GT/s systems. This Synopsys webinar explains how designers can overcome these challenges by accounting for PCIe 6.0 system-level co-design in pre-silicon. In addition, the Synopsys webinar highlights the importance of pre-silicon validation for overall system integration, performance and compliance.

Back to Events

Newsletter Signup

Keep up to date with our latest news and events.

    Techworkshub Limited, 1 George Square, Glasgow G2 1AL

    Privacy Policy

    Restricted Content

    This content is restricted to registered users. To view the content please either login or register below.

    Login in Register

    Restricted Content

    This content is restricted to registered users. To view the content please either login or register below.

    Login in Register