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FPGA Frontrunner Meet & Greet

March 23, 2022 @ 9:30 am - 6:30 pm

NMI is all about sharing knowledge and creating communities. The FPGA Front Runners exists to share knowledge, best practice and to create a community around FPGAs and ASIC development.

Each event is about networking, meeting colleagues, grabbing a coffee and some cake and listening to presentations from suppliers and your peers.

The event is designed to create a community of likeminded engineers, and is run by members for members and the subjects and presentations are chosen by the members, so remain valid.

The ultimate aim is to create a better awareness of FPGAs & ASICs in the UK, drive best practice, identify common issues and challenges and work together to resolve them. This first event is designed to bring together the community, discuss the current market conditions around FPGAs, the issues and technical challenges each member needs to overcome. Look at the skills shortages and what is needed to improve the engineers use of FPGAs. Everyone is welcome and we encourage you to attend and get involved.

Events are planned to run quarterly, with other events or webinars in between as suggested by the community.

Steve Drew

NMI Electronic Systems

Steve has over 30 years of semiconductor, electronics and design industry experience. Starting his career at Avnet, he became one of their youngest product managers – looking after Xilinx for the UK. Steve subsequently worked at a number of niche component distributors...

FPGA’s became his thing in the 1990’s and Steve worked with all the FPGA manufacturers except Altera. Moving on from component distribution Steve has worked at component kitting and PCB assembly companies, and having worked for large multinational companies and smaller privately owned businesses, has given Steve a wide view of the component market place and the challenges faced by companies, and having run his own manufacturing consultancy since 2020 has given him an understanding of the small business sector.

Steve loves the electronics industry and technology in general, is passionate about UK manufacturing and how we can build more here instead of losing it to offshore competition, is a champion of startup’s and innovation. And if you want an opinion on something, just ask him

Adam Taylor

Founder, Adiuvo Engineering

Adam Taylor is a world recognised expert in design and development of embedded systems and FPGA’s for several end applications.  Throughout his career, Adam has used FPGA’s to implement a wide variety of solutions from RADAR to safety critical control systems (SIL4) and satellite systems.

He also had interesting stops in image processing and cryptography along the way. Adam has held executive positions, leading large developments for several major multinational companies. For many years Adam held significant roles in the space industry he was a Design Authority at Astrium Satellites (Now Airbus Space) Payload processing group for six years and for three years he was the Chief Engineer of e2v Space Imaging, being responsible for several game changing projects.


FPGAs are Adam ‘s first love, he is the author of numerous articles and papers on electronic design and FPGA design including over 400 blogs and 25 million plus views on how to use the Zynq and Zynq MPSoC for Xilinx.
Adam is Chartered Engineer, Senior Member of the IEEE, Fellow of the Institute of Engineering and Technology, Visiting Professor of Embedded Systems at the University of Lincoln and Arm Innovator, Edge Impulse Ambassador, he is also the owner of the engineering and consultancy company Adiuvo Engineering and Training.

Presentation: PYNQ – FPGA with Python

Myrtle Shah

Founder, Chipflow

Myrtle is an engineer and founder at ChipFlow, working on a reliable end-to-end open source flow for building chips. They are also the lead developer of nextpnr, an open source FPGA place and route tool, and the creator of the Project Trellis bitstream documentation and open flow for Lattice ECP5 FPGAs. 

...They enjoy walking and gardening in their spare time when they need to get away from computers..

Presentation: OS RISC V SoC built with Python

By combining Amaranth, a Python-based framework for describing and constructing hardware, with a stack of other open source tools, it's possible to build complex SoCs not just for FPGAs but also taped out as chips. We'll be having a look at the ecosystem for both as it stands today; some examples of projects using it including the journey to a tapeout-ready, Linux-capable RISC-V SoC on the Skywater 130nm process; and what the future of open tooling might look like.

Tony Holmes

Cadence

Tony started his career at Digital Equipment in the design & development of Computer Special Systems then moved into the Design and Development of High Performance Bridge Routers...

...followed by creating a System Level Testing group to test these Bridge/Routers in complex networking scenarios.

Tony moved to Quickturn Design Systems before Quickturn merged with Cadence Design Systems. Tony is a Technical Director at Cadence Design Systems with a long history of focussing primarily on HW based verification using Emulation and FPGA Prototyping.

Tony has responsibility for Technical Engagements for any HW based verification project/engagement within EMEA.

Presentation: 500M Gates in FPGAs (FPGA Prototyping)

A few years ago the concept of running Billions of gates on an FGPA System would have been mind boggling.

This Cadence Presentation will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification.

We will review the traditional prototyping challenges of complex SoCs using a 5G AI-enabled mobile SoC case study—RTL changes required for clock management, memories, interfaces, multi-FPGA partitioning, and multi-user support.

You will learn how the Protium X2 features and solutions solve these challenges while accelerating the hardware/software co-design verification schedule.

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